The present invention relates to drives for display panels, such as plasma display panels and electroluminecsent panels, and more particularly to capacitive load drives capable of recovering charging and discharging power of electrostatic capacitance of a display panel. More specifically, the present invention relates to energy recovering type capacitive load drives for applying pulses to capacitive loads, which is capable of operating faster than prior art systems, with less reactive power and high efficiency.
Among capacitive loads requiring pulses for driving are display panels, such as plasma display panels, electroluminescent panels and liquid crystal panels, which are used as image displays for data terminal units, personal computers and television sets.
As a typical example of the drive, one which can reduce the reactive power of a plasma display panel drive circuit will be described hereinunder.
A plasma display panel is simple in construction and readily capable of increasing its display face area. As another merit, for a substrate of the panel it is possible to use inexpensive soda glass finding extensive applications to window glasses and the like.
The plasma display panel is fabricated by using two transparent insulating substrates of soda glass or the like, forming partitioning walls partitioning electrodes or display unit pixels on the substrates, and bonding together the substrates with these structures formed thereon.
Usually, the partitioning walls have a height of about 0.1 mm, and the transparent insulating substrates have a thickness of about 3 mm. Thus, it is possible to obtain a display which is very thin and light in weight.
With the above merits, plasma display panels are about finding applications particularly to recently extremely advanced personal computers and office work stations and also large size wall televisions which are expected to be advanced.
In dependence on the panel structure, plasma displays are largely classified into a DC type and an AC type. The DC type is so called, because its electrodes are in direct contact with discharge gas, and once discharge is caused, it carries DC current continuously. In the AC type, an insulating layer intervenes between electrodes and discharge gas. In this type of plasma display, a pulse current is caused, in response to voltage application, to flow for a short period of about 1 microsecond before it is converged. In this case, the current flow is restricted by the electrostatic capacitance of the insulating layer. The insulating layer serves as a capacitor, and by AC pulse application recurring pulse light emission is caused for display. This is why the AC type is called as such.
The DC type is simple in construction. However, this type of plasma display has a drawback that electrodes are directly exposed to the discharge and therefore greatly worn out, and it is difficult to ensure long electrode life. The AC type, on the other hand, can ensure long electrode life because the electrodes are covered by the insulating layer, although the formation of the insulating layer requires extra time and expenditure. In addition, a function called memory can be readily realized, which permits high intensity light emission. Thus, development of the AC type is recently in rapid progress.
An AC memory type plasma display panel structure will now be described, and then a method of driving the panel and a prior art drive circuit will be described.
As the AC memory type plasma display panel structure, one which is shown in Japanese Laid-Open Patent Publication No. 7-295506 will now be described with reference to FIGS. 7A and 7B. The AC memory type plasma display panel structure shown in FIGS. 7A and 7B has an electrode structure of generally called surface discharge type, and is an example of display panel, to which the capacitive load drive according to the present invention is applied as will be described later in detail. FIG. 7A is a plan view, and FIG. 7B is a sectional view taken along line x-x' in FIG. 7A.
Referring to FIGS. 7A and 7B, the illustrated plasma display panel structure comprises a first insulating substrate 11 of soda glass having a thickness of about 3 mm, a second insulating substrate 12 also of soda glass having the same thickness of about 3 mm, sustained discharge electrodes 13a of a transparent NESA film provided on the first insulating substrate 11, scanning electrodes 13b of the same transparent NESA film, metal electrodes 13c of a thick silver film or the like provided on the transparent sustained discharge and scanning electrodes 13a and 13b for supplying sufficient current thereto, column electrodes 14 of a thick silver film or the like provided on the second insulating substrate 12, discharge gas spaces 15 filled with discharge gas composed of He and Ne in a ratio of 7:3 and also 3% of Xe and under a total pressure of 500 Torr, a thick partitioning wall structure 16 of glass provided on an insulating layer 18a such as to secure the discharge gas spaces and defining pixels, a phosphor 17 composed of Zn.sub.2 SiO.sub.4 :Mn laminated on an insulating layer 18b for converting ultraviolet light by discharge of the discharge gas to visible light, the insulating layer 18a formed as a thick film of transparent glaze covering the sustained discharge, scanning and metal electrodes 13a, 13b and 13c, and a protective layer 19 of MgO having a thickness of 1 .mu.m for protecting an insulating layer 18a covering the electrodes 13a, 13b, 13c and also the insulating layer 18a against the discharge.
Referring to FIG. 7A, sections defined by the vertical and horizontal portions of the partitioning wall structure 16 are pixels 20.
Referring to FIG. 8, pixels at the intersections of scanning electrodes SSi (i=1, 2, . . . , m) and column electrodes DDj (j=1, 2, . . . , m) are labeled aij. By providing the phosphor 17 in FIG. 7B as red, green and blue phosphors for the individual pixels, a plasma display is obtainable which permits full color display. Display may be made on either the upper or the lower surface of the plasma display shown in FIG. 7B. In this example, suitably the display is made in the lower surface. This is so because in this case a higher aperture factor is obtained, and light-emitting phosphors can be directly viewed, i.e., a higher light intensity is obtainable.
FIG. 8 is a plan view showing only the electrodes of the plasma display panel shown in FIGS. 7A and 7B. Referring to FIG. 8, designated at 10 is the plasma display panel, at 21 a sealed section obtained by sealing together the first and second insulating substrates 11 and 12 with discharge gas sealed in the inside, at CC1, CC2, . . . , CCm the sustained discharge electrodes 13a, at SS1, SS2, . . . , SSm the scanning electrodes 13b, and at DD1, DD2, . . . , DDn the column electrodes 14.
An actual plasma display panel comprises, for instance, 480 scanning electrodes SS1, SS2, . . . , SSm, 480 sustained discharge electrodes CC1, CC2, . . . , CCm and 1,920 column electrodes DD1, DD2, . . . , DDn. The inter-pixel pitches are 0.35 mm between adjacent column electrodes and 1.05 mm between adjacent scanning electrodes. The distance between each scanning electrode and each column electrode is 0.1 mm.
A method of providing a gradation display on the above plasma display will now be described.
In the plasma display panel, unlike other devices, it is difficult to obtain high intensity gradation display by changing the applied voltage, because the applied voltage and the light intensity are not linearly related to each other. Usually, gradation display is obtained by controlling the number of light emission times. Particularly, a sub-field method to be described in the following is used for the high light intensity gradation display.
FIG. 9 is a view for describing a drive sequence in the sub-field method. In the graph, the ordinate axis is taken for scanning electrodes, and the abscissa axis is taken for time. One image frame is fed in one field. The field time varies with different computers and broadcast systems, but in many cases it is set to be in a range of 1/50 to 1/75 second.
As shown in FIG. 9, in the gradation image display on the plasma display panel, one field is divided into k sub-fields (i.e., 6 sub-fields SF1 to SF6 in the case of FIG. 9). As will be described later in connection with FIG. 10, each sub-field consists of a write time for writing data under control of preliminary discharge pulses, preliminary discharge erase pulses, scanning pulses and data pulses, and a sustained discharge time for display light emission.
The intensity of light emitted from each pixel is controlled by weighting or multiplying the number of times of the sustained discharge light emission from each pixel in each sub-field by 2.sup.n as: ##EQU1##
In formula (1), n is the serial number of the sub-field. That is, 1-st sub-field is the lowest light intensity sub-field, and k-th sub-field is the highest light intensity sub-field. L1 is the light intensity of the lowest light intensity sub-field. a.sub.n is a variable taking a value of either "1" or "0", and is "1" when light is emitted and "0" when not so in the pertinent pixel in n-th sub-field. The light intensity can be controlled by selecting whether light from each sub-field is to be "on" or "off".
FIG. 9 shows the case where k is 6. Where color display is made with a red, a green and a blue pixel as a set, gradation display 2.sup.k =2.sup.6 =64 gradations may be made in each color. The color display can be made in 64.sup.3, i.e., 262,144 different colors (including black color).
Where k is 1, one field consists of one sub-field, and two-gradation display (i.e., "on"-or-"off" display) may be made in each color.
Drive waveforms will now be described. FIG. 10 is a view showing an example of drive voltage waveforms and a light emission waveform in a sub-field in the prior art plasma display panel shown in FIGS. 7 and 8.
Referring to FIG. 10, labeled (A) is the waveform of voltage applied to the sustained discharge electrodes CC1, CC2, . . . , CCm.
Labeled (B) is the waveform of voltage applied to the scanning electrode SS1.
Labeled (C) is the waveform of voltage applied to the scanning electrode SS2.
Labeled (D) is the waveform of voltage applied to the scanning electrode SSm.
Labeled (E) is the waveform of voltage applied to the column electrode DD1.
Labeled (F) is the waveform of voltage applied to the column electrode DD2.
Labeled (G) is the waveform of light emission from pixel all.
The shaded pulses in the waveforms (E) and (F) indicate that their presence or absence is determined by whether data to be written is present or not.
As data voltage waveforms, FIG. 10 shows the case where data is written in pixels all and a22. As for the pixels in the 3-rd and following lines, it is indicated that display is made in dependence on whether data is present or not.
Sustained discharge pulses 31 and preliminary discharge pulses 36 are applied to the sustained discharge electrodes CC1, CC2, . . . , CCm.
Scanning pulses 33 are applied in line sequence to the scanning electrodes SS1, SS2, . . . , SSm in independent timings in addition to common pulses, i.e., the sustained discharge pulses 32, erase pulses 35 and preliminary discharge erase pulses 37. Data pulses 34 are applied in synchronism to the scanning pulses 33 to the column electrodes DDj (j=1, 2, . . . , n) when light emission data is present.
The operation of the prior art plasma display panel shown in FIGS. 7 and 8 will now be described. The discharge of the pixels which have been "on" in the immediately preceding sub-frame are erased by an erase pulse 35. Then, forced discharge of all the pixels is caused once by a preliminary discharge pulse 36. The preliminary discharge is then erased by the preliminary discharge erase pulse 37. Now, write discharge can be readily caused by the scanning pulses which are subsequently applied.
After the preliminary discharge has been erased, write discharge is caused by applying scanning pulses 33 and data pulses 34 at the same timings between the scanning electrodes and the column electrodes. Subsequently, sustained discharge is held between each sustained discharge electrode and the associated scanning electrode by sustained discharge pulses 31 and 32.
When sole scanning pulse 33 or sole data pulse 34 is applied, no write discharge is caused, and also no subsequent sustained discharge is caused. Such a function is called memory function, and the intensity of light emitted in each sub-field is controlled by the number of times of causing the sustained discharge.
Now, the drive circuit of the prior art plasma display panel will be described with reference to FIG. 11. The circuit comprises a plasma display panel pixel group 41, a generator 42 for generating preliminary discharge pulse, a pulse generator 43 for generating the sustained discharge electrode side sustained discharge pulses 31 and including a energy recovery circuit, a pulse generator 44 for generating the scanning side erase pulses 35 and preliminary discharge erase pulses 37, a scanning pulse generator 45, and a pulse generator 46 connected via a mixer 47 to the scanning electrodes, for generating the scanning electrode side sustained discharge pulses 32 and including a energy recovery circuit. The mixer 47 mixes the scanning electrode side sustained discharge pulses and the scanning pulses. Designated at TP1 is an output terminal of the sustained discharge electrode side sustained discharge pulse generator 43 or the scanning electrode side sustained discharge pulse generator 46.
Since the electrostatic capacitance of the plasma display panel is high, a commonly termed energy recovery circuit for recovering the charging and discharging power of the electrostatic capacitance is used to recover the charging and discharging power of the sustained discharge pulses, and a circuit consuming less power is used for the sustained discharge and scanning electrode side sustained discharge pulse generators 43 and 46 (see, for instance, Japanese Laid-Open Patent Publication No. 61-132997).
The basic circuit and operation of this first prior art will now be described. FIG. 12 is a circuit diagram showing the basic construction of the prior art sustained discharge pulse generating circuit with a power recovering circuit, for generating sustained discharge pulses.
Referring to FIG. 12, the circuit comprises a DC power supply output capacitor C100, external capacitance C101 including floating capacitance in the circuit, C102 equivalent electrostatic capacitance between each scanning electrode and the associated sustained discharge electrode in the plasma display panel, high voltage side switches S100, S101, S102 and S103, diodes D100, D101, D102 and D103 and a energy recovery coil L100. Designated at TP1 is the output terminal of the sustained discharge or scanning electrode side sustained discharge pulse generator 43 or 46, and at TP2 a terminal, which a DC power supply providing sustained discharge pulse voltage (VS) is connected to.
The operation of the circuit shown in FIG. 12 will be briefly described with reference to a timing chart shown in FIG. 13. For providing the sustained discharge pulse voltage, at instant T100 the switch S103 is turned off while the switch S100 is turned on. As a result, the external capacitance C101 and the panel capacitance C102 are charged through the coil L100.
At instant T101, the voltage at the terminal TP1 exceeds the DC power supply voltage (VS) at the terminal TP2, whereupon the diode D102 is turned on to clamp the voltage at the terminal TP1 to the voltage (VS) at the terminal TP2.
If the switch S100 is held "on" at this time, current would be caused through the closed circuit of the coil L100, the diode D102 and the switch S100 by the electromotive force of the coil L100. This power would be wasted in the closed circuit. Accordingly, the switch S100 is turned off in accurate synchronism to the instant T101, at which the voltage at the terminal TP1 exceeds the voltage at the terminal TP2. Consequently, the energy having been stored in the coil L100 is recovered in the capacitor C100 connected to the terminal TP1 through the coil L100, the diode D100, the capacitor C100 and the diode D101.
At subsequent instant T101 when the voltage at the terminal TP1 exceeds the voltage at the terminal TP2, the switch S102 is closed to connect the DC power supply through the terminal TP1 and fix the voltage at the terminal TP1 the sustained voltage pulse voltage (VS).
At subsequent instant T102, the switch S102 is turned on while turning on the switch S101 to remove the sustained discharge pulse voltage. As a result, the voltage at the terminal TP1 is reduced to zero voltage through the coil L100. At subsequent instant TP1 when the voltage at the terminal TP1 becomes lower than zero voltage, the diode D103 is turned on, whereupon the voltage at the terminal TP1 is clamped to zero voltage.
If the switch S101 is held "on" at this time, current would flow through the closed circuit of the coil L100, the switch S101 and the diode D103 due to the electromotive force of the coil L101, and this power would be wasted in the closed circuit. Accordingly, the switch S101 is turned off in exact synchronism to the instant T103 when the voltage at the terminal TP1 becomes lower than zero voltage. By so doing, the energy having been stored in the coil L100 is recovered in the capacitor C100 connected to the terminal TP2 through the coil L100, the diode D100, the capacitor C100 and the diode D102.
While in this prior art positive polarity pulse voltage is generated, in the case of the prior art drive waveforms shown in FIG. 10 negative polarity pulse voltage is used. In this case, the power supply terminal TP2 may be grounded so that the grounded circuit part is connected to the negative side of the DC power supply. In this case, the external capacitance C101 and the electrostatic capacitance C102 of the panel may be equivalently grounded at one end as shown in FIG. 12 as is usual.
As described above, for efficient energy recovery it is necessary to accurately control the timings or instants of turning off the switches S100 and S101. Inaccurate timing control would increase the power loss in the energy recovery circuit and extremely deteriorate the energy recovery efficiency and, in the worst case, would result in burning of the diodes D102 and D103 and the switches S100 and S101.
The above timing control is efficient in the case of the electroluminescent panel described as an embodiment in the above Japanese Laid-Open Patent Publication No. 61-132997, in which the operation may be relatively slow. In this electroluminescent panel the rise or fall time of data pulses applied to the column electrodes is several microseconds or above. Such rise and fall time permits the use of power MOS FET elements with operation delay of about 0.1 microsecond to realize as the switches S100 and S101 those which can be held "on" for only several microseconds, a time corresponding to the above rise or fall time.
However, the situation is different with the plasma display panel or the like, which is required to perform very fast operation compared to the electroluminescent panel. In the plasma display panel, the rise or fall time of sustained discharge pulses is about 0.2 to 0.5 microsecond. A high power, high breakdown voltage switch, which can perform sufficiently fast operation (preferably with operation delay time of 0.1 microsecond or below) and can be held "on" accurately only for such short rise or fall time, is not available or expensive, if any.
Therefore, the circuit construction shown in the above Japanese Laid-Open Patent Publication No. 61-132997 cannot sufficiently meet the requirements of the plasma display panel.
Japanese Laid-Open Patent Publication No. 63-101897 and Japanese Laid-Open Patent Publication No. 8-160901 show drives of energy recovery type for supplying pulses to plasma display panels. Such drives will now be described as second prior art.
FIG. 14 is a circuit diagram showing the basic circuit in this second prior art. Referring to FIG. 14, the circuit comprises switches S11 to S14, diodes D11 to D14, a energy recovery coil L1, electrostatic capacitance of the plasma display panel as load, and a energy recovery capacitor C100 having 100 times the electrostatic capacitance C2 or more. Designated at TP1 is an output terminal of the sustained discharge or scanning electrode side sustained discharge pulse generator as shown in FIG. 11. Designated at TP2 is a terminal connected to a power supply for providing the sustained discharge pulse voltage.
This prior art circuit, like the circuit in the first prior art as shown in FIG. 11, will be described as positive polarity pulse generating circuit.
Referring to FIG. 15 which shows the operation of switches and output voltage waveform in this circuit, in the steady state of pulse supply to the plasma display panel, the terminal voltage across the capacitor C10 is approximately one half the voltage (VS) at the terminal TP2.
To cause pulse rise, the switch S14 which has been clamping the voltage at the TP1 to the ground voltage is turned off while turning on the switch S11. As a result, current is caused to flow in a series resonance state from the capacitor C10 through the switch S11, the diode D11 and the coil L1. When the voltage at the terminal TP1 becomes maximum with the resonance of the coil L1 and the electrostatic capacitance C2, the switch S13 is turned on to clamp the voltage at the terminal TP1 to the voltage at the terminal TP2, i.e., the voltage (VS) of the sustained discharge pulse voltage source.
To cause pulse fall, the switches S11 and S13 are turned off while turning on the switch S12. As a result, the voltage at the terminal TP1 is caused to fall. Like the pulse rise case, when the voltage at the terminal TP1 becomes minimum with the resonance of the coil L1 and the electrostatic capacitance C2, the switch S14 is turned on to clamp the voltage at the terminal TP1 to the ground voltage.
While it has been noted that the capacitance of the capacitor C10 is 100 times the electrostatic capacitance C2 of the panel or more, this is by no means limitative; for instance, it is sufficiently comparable with the electrostatic capacitance C2 of the panel (see, for instance, Japanese Laid-Open Patent Publication No. 8-137432.
In this second prior art, as shown in FIG. 15, the "on" time of the switches S11 and S13 need not be limited to the rise or fall time of the output pulse. More specifically, the "on" time may be extended without any operational problem up to the end of the subsequent clamp time (from instant T12 to instant T13).
It is thus possible to readily realize a plasma display panel by using prior art MOS FETs or the like even with as short rise or fall time as 0.2 to 0.5 microsecond.
In the second prior art as shown above, however, as is seen from the voltage waveform at the terminal TP1 shown in FIG. 15, a jump voltage .DELTA.V is always caused when the clamp circuit is turned on at the rising and falling of pulse (i.e., at instants T12 and T14) due to power loss in the energy recovery circuit, which is constituted by power MOS FETs or the like having finite "on" resistance.
Therefore, at the instants T12 and T14 a rash current is caused through the clamp circuit, resulting in power loss in the switches S13 and S14 and also noise generation.
Japanese Laid-Open Patent Publication No. 8-152865 discloses a drive of energy recovery type which supplies pulses to a plasma display panel. This drive will now be described as third prior art. FIG. 16 is a block diagram showing the basic construction of the third prior art.
Referring to FIG. 16, a sustained discharge electrode side sustained discharge pulse generator 48 is used in lieu of the sustained discharge and scanning electrode side sustained discharge pulse generators 43 and 46 used in the prior art shown in FIG. 11. Designated at TP21 and TP22 are output terminals of the sustained discharge pulse generator 48.
FIG. 17 is a circuit diagram showing the sustained discharge pulse generator 48. Referring to FIG. 17, designated at TP3 is a terminal connected to a power supply for supplying the sustained discharge pulse voltage, at TP21 and TP22 sustained discharge pulse output terminals as shown in FIG. 16, at S21 to S26 switches for clamping the voltages between the output terminals TP21 and TP22 to the ground voltage or the sustained discharge pulse voltage, at S25 and S26 energy recovery switches, at L21 a energy recovery coil, and at D25 and D26 energy recovery diodes.
This third prior art, unlike the preceding first and second prior arts, will be described as a circuit which generates negative polarity sustained discharge pulses.
Referring to FIG. 18, which is a waveform chart illustrating operation of switches and showing output voltage waveform of the circuit, at instant T20 the switches S21 and S24 are "on" while the switch S25 is "off". Also, a negative polarity sustained discharge pulse voltage (-VS) prevails at the terminal TP22.
When the switches S21, S24 and S25 are turned off while the switch 26 is turned on at subsequent instant T21, the electrostatic capacitance C2 of the panel turns to be discharged through the switch S26, the diode D26 and the coil L21, thus causing resonant current through this circuit.
When the resonant current has been ended, the voltage at the terminal TP22 rises at instant T22 as shown as the voltage waveform thereat in FIG. 18. At this instant, the switches S22 and S23 are turned on to clamp the voltage at the terminal TP21 to the sustained discharge pulse voltage (-VS) and the voltage at the terminal TP22 to zero voltage.
In this third prior art, as shown in FIG. 18, the "on" time of the switches S25 and S26 need not be limited to the rise or fall time of the output pulse, and may be extended without any operational problem up to the end of the subsequent clamp time (of 1 to 5 microseconds or more).
It is thus possible to realize a plasma display panel by using prior art power MOS FETs even with as shot rise or fall time of 0.2 to 0.5 microsecond.
In the third prior art, however, as is seen from the voltage waveforms at the terminals TP21 and TP22 as shown in FIG. 18, a jump voltage .DELTA.V is always caused when the clamp circuit is turned on at the rising and falling of pulse (i.e., at instant T22 and T24) due to power loss in the energy recovery circuit, which is constituted by power MOS FETs or the like having finite "on" resistance.
Therefore, at the instants T22 and T24 a rash current is caused through the clamp circuit, resulting in power loss in the switches S21 to S24 and also noise.
As has been described, the above prior arts have the following problems.
In the first prior art, it is difficult to obtain highly efficient energy recovery operation during high rate pulse generation.
In the second and third prior arts, the operation of switches for voltage clamping causes a rash current to result in power loss and noise generation.